Non-volatile floating-gate MOS memories are well known in the industry. In such devices, the conductive state of the transistor memory cell is determined by the voltage on an associated floating gate.
Designs have been proposed which facilitate the erasure and resetting of the voltages on these floating gates. For example, in U.S. Pat. No. 4,119,995 (issued Oct. 10, 1978 to Simko and assigned to Intel Corporation) the floating gate is controlled by separate programming and erasure gates which are disposed above the floating gate and insulated therefrom by an oxide layer. The floating gate voltage is programmed by electron injection from the substrate. The charge on the floating gate is erased by causing electrons to flow from the floating gate up to the erasing gate.
Other designs have been proposed which utilize charge transfer between the floating gate and one or more control gates to both erase and program the floating gate (i.e., in these designs the tunnelling or avalanche of electrons from a structure other than a substrate region is used to set the voltage of the floating gate). See e.g. Lee, "A New Approach for the Floating-Gate MOS Nonvolatile Memory", Applied Physics Letters, Vol. 31, No. 7, October 1977, pp. 475-476. This paper discloses a single control gate separated from the floating gate by a poly-oxide layer. When the control gate is biased positive for writing, electron flow is induced from the floating gate to the control gate. Since this flow is greater than the flow of electrons from the substrate to the floating gate, the floating gate accumulates positive charge. When the control gate is ramped negative to erase, the floating gate accumulates negative charge. See also U.S. Pat. Nos. 4,099,196; 4,274,012; 4,300,212; and 4,314,265 (issued 7/4/78, 1/24/79, 10/10/81 and 2/2/82, respectively, to Simko) which disclose erasable PROM's wherein a programming gate is disposed below the floating gate and an erasure gate is disposed above the floating gate. The devices are programmed by inducing electron flow from the program gate to the control gate and are erased by inducing electron flow from the floating gate to the erasing gate. In all four patents, the surface of one or more of the gates is roughened in order to enhance the induced electric fields. This promotes electron flow through the oxide layers separating the gates.
Among the materials which have charge injection properties is the so-called dual electron injector structure (DEIS), which is a layer of Si0.sub.2 having excess silicon crystals on its upper and lower surfaces. This structure is disclosed in U.S. Pat. No. 4,104,675 (issued to DiMaria and assigned to the assignee of the present application). DEIS is generally formed by a chemical vapor deposition process which induces extra silicon crystal growth both prior and subsequent to the formation of an otherwise normal Si0.sub.2 layer. Several patents specifically disclose the use of a DEIS layer as the injector structure for a non-volatile memory. See e.g., U.S. Pat. No. 4,336,603 (issued 6/22/82 and assigned to the assignee of the present application). This patent discloses a single control gate which injects electrons into the floating gate through a DEIS layer.
This DEIS layer has also been incorporated in providing the injector structure for the non-volatile component of a non-volatile dynamic RAM. See e.g. U.S. Pat. No. 4,446,535 (issued 5/1/84 to Gaffney et al and assigned to the assignee of the present application), which discloses the use of DEIS to construct a single control gate of a non-volatile element associated with (i.e. storing the "latent image" of) a dynamic RAM cell (DRAM). Such non-volatile DRAMs are also disclosed in U.S. Pat. Nos. 4,449,205 (issued 5/15/84 to Hoffman); 4,363,110 (issued 12/7/82 to Kalter et al); 4,432,072 (issued 2/14/84 to Chao et al) and 4,375,085 (issued 2/22/83 to Grise et al), all of which are assigned to the assignee of the present application. In each of these patents, the data stored on the floating gate is erased before new data can be stored thereon. This extra operational step adversely affects the operational speeds attainable in these memories.